Advanced automation in formal verification of processors

This thesis addresses automation and enhanced user support in functional verification of digital systems with a special focus on processors. Verification is an important issue in the design process of digital systems. In contrast to traditional simulation based methods, formal verification can provide a mathematical correctness proof. But, up to today, these methods are difficult to use in practice, without a strong background in formal techniques. This thesis aims at improving the usability and increasing the productivity of formal hardware verification.