Optimization algorithms for dynamically reconfigurable embedded systems

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Reconfigurable hardware components such as FPGAs (Field Programmable Gate Arrays) are used more and more in embedded systems, since such components offer a sufficient capacity for a complete SoC (System on a Chip) or even NoC (Network on a Chip). In order to use efficiently the dynamic reconfiguration possibility on such components, one needs a support in the form of an operating system to manage both software and reconfigurable hardware. For this support, a suitable reconfigurable hardware model and optimization methods are required. The goal of this thesis is the investigation of optimal strategies, methods and architectures for controlling and using the newest and future generations of reconfigurable hardware.