Formal Verification of Circuits

Meer over het boek

The book delves into the challenges of formal verification in circuit design, particularly as the complexity of circuits increases with millions of transistors. It emphasizes the limitations of pure simulation and the benefits of leveraging regular structures in designs for easier verification. Highlighting the use of Word-Level Decision Diagrams (WLDDs), the text explains how these graph-based representations facilitate the verification of functions with a Boolean range and integer domain, making the process more efficient for complex designs like ALUs and multipliers.