Manish Jain Boeken

The High Performance (HiPer) Switch Architecture offers a detailed engineering approach modeled in C++ and VHDL, showcasing advanced traffic management for ATM networks. It achieves a remarkably low Cell Loss Ratio of 1.0x 10-8 with a 64-cell buffer under a high-traffic scenario. The design, implemented in a 0.5 m CMOS VLSI process, demonstrates a peak throughput of 200 Mbps per output port. The architecture effectively manages diverse applications such as voice, video, and data, emphasizing traffic and congestion control strategies to meet specified quality of service (QoS) requirements.

The book focuses on the design of a solitary chip Asynchronous Transfer Mode (ATM) switch utilizing Very Large Scale Integration (VLSI) technology. It explores various buffering techniques to address conflict issues in ATM switching and presents a VHDL model to validate functionality. An 8x8 switch design is detailed, employing a 0.5 m CMOS VLSI process, achieving a peak throughput of 200 Mbps per output port. The text emphasizes the importance of managing network traffic and resource allocation for diverse applications, ensuring quality of service (QoS) for users.