Secure testing of VLSI cryptographic equipment

The physical security of crypotgraphic equipment requires non-accessibility of sensitive information and concurrent monitoring of correct hardware functionality. This thesis describes a new built-in self-test scheme that reconciles the need for testability of VLSI circuits with the security requirements. An off-line testing scheme provides a good fault coverage, and an on-line check is well-suited to detect falure concurrently to the normal encryption operation.