Indirect code generation for VLIW architectures and a hardware optimization algorithm

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Many modern embedded applications, such as mobile communication and multimedia, demand high computing performance and low power consumption. Contemporary processor architectures, particularly Very Long Instruction Word (VLIW), can meet these needs by exploiting instruction-level parallelism to enhance computation speed while reducing power usage. However, traditional compilers often fail to effectively utilize the unique characteristics of VLIW architectures, resulting in subpar application performance. This thesis proposes an indirect code generation method for VLIW architectures, translating efficient compiled assembly code from RISC architectures into target VLIW assembly. The process involves three steps: first, compiling the source code for a RISC architecture using an optimizing compiler; second, a pre-processing step that optimizes RISC assembly and translates it into a RISC-like assembly closely aligned with the target VLIW architecture; and third, a post-processing step that applies VLIW-specific optimizations. This approach allows for the benefits of VLIW processors to be realized while leveraging the efficiency of traditional RISC compiler techniques. Additionally, the thesis introduces an algorithm to support hardware exploration of the target VLIW architecture using a fuzzy control system to identify optimal application-specific processor configurations. To validate this indirect code generation and hardware explo